Similar to modern software development, the efficient creation of complex system-on-chip (SOC) designs relies on reuse of pre-designed intellectual property (IP) components. These pre-designed IP components are often referred to as cores. A core may be combined with other cores to develop more complex SOC designs. To support testing of the SOC designs, each core may have a wrapper that isolates the core from SOC design. The wrapper enables the core to be tested independently from the SOC design in which it is used.
A test access mechanism (TAM) may be embedded on the SOC to communicate test patterns and test responses between the input/output (I/O) pins of the SOC design and the core wrappers. IEEE 1500 defines a standard architecture for enabling the testing of cores in a SOC design. The core test language (CTL) defined in the IEEE 1500 standard describes the wrappers, the test patterns, and the test responses for testing cores. The TAM may receive the test patterns from and communicate the test responses to an automated test equipment (ATE). The ATE may be used to test multiple devices in parallel by supplying the test patterns and receiving the test responses from each of the multiple devices. The ATE may then compare the test responses with expected responses to generate the results of the test.
Testing multiple devices in parallel enables a reduction in testing costs while maximizing the production capacity of the devices. As the number of devices to be tested in parallel increase, the computational resources required by the ATE to perform the communications and comparison operations similarly increases. Also, the total bandwidth of communication between the ATE and the multiple devices increases with the number of devices being tested in parallel.